This invention relates to an integrated circuit which is fully protected from UV radiation, being of a type implemented in MOS technology over a semiconductor substrate and which includes at least one memory cell with a floating gate transistor having drain, source, and gate terminals, and a metallic shield embedded in the semiconductor substrate and covering said cell.
The field of application of this invention relates, particularly but not solely, to CMOS technology integrated circuits incorporating EPROM memory cells with floating gate MOS transistors, and the description to follow will make reference to this field of application for simplicity of illustration.
As is known, non-volatile memory cells of the EPROM type are written electrically and cleared by means of ultraviolet beams. It is also well recognized that in the manufacture of integrated circuits incorporating EPROM memory cells, allowance must be made for spare or redundant portions, i.e. portions which can replace memory areas rendered inoperative by any designing flaws. To permit appropriate selection of such redundancy (to fix the defects of a particular chip), some technique must be used to permanently encode the necessary information on-chip. This allows access paths to be established which either enable or inhibit readout of selected memory areas.
An old technique for such selection used thin-film fuse elements: each fuse, when blown, would provide a permanent memory corresponding to one bit of data. However, actual fuses have many disadvantages, so that such fuses have normally been replaced by memory cells of the EPROM type, i.e. floating gate MOS devices. Such cells are inherently and unavoidably responsive to UV radiation: when UV photons are absorbed in or near the floating gate, the resulting carriers will be "hot", i.e. sufficiently energetic to travel through a dielectric. Thus, when exposed to UV radiation, the floating gates may lose their electric charge and, consequently, the information represented thereby. (For this reason, ultraviolet flood illumination is commonly used to erase EPROMs.)
In such fuse-like functional applications of EPROM cells, the EPROM cell must therefore be protected against ultraviolet light. This is particularly necessary because EPROM circuits themselves will normally be exposed to UV by users who wish to erase them. Thus, if redundancy is to be useful in repairing EPROM chips, the redundancy selection data must not be wiped out by the UV exposures normally applied by users!
The prior art has therefore proposed to screen the EPROM cell by means of a metallization shield, e.g. one formed from an aluminum thin film connected to the substrate of the semiconductor IC. That is, in this approach the EPROM cell is covered with a squared up conductive layer of aluminum which is connected along three sides to the silicon substrate, as previously made conductive by an appropriate doping step. In this way, the UV radiation will be reflected from the thin film metal, and the corresponding EPROM cell may be regarded as an UPROM (Unerasable Programmable ROM) structure.
Some implementations of UPROM cells have had the drawback that at least one side of the aluminum covering is left exposed, in order to permit the drain, source, and floating gate terminals of the MOS transistor in the memory cell to be biased. As a result, ultraviolet light is admitted inside through this unconnected side to the substrate and allowed to propagate therein until it indirectly reaches the floating gate. As a consequence, the immunity of a cell so protected to UV radiation is bound to only last a few weeks.
To obviate this drawback, the prior art has proposed that meanders of suitably doped silicon be formed on the semiconductor for communicating the bias to the aforesaid drain, source and gate terminals. (Along these meanders, the ultraviolet light is repeatedly reflected and absorbed such that it can no longer reach the floating gate with sufficient intensity to remove the charge therefrom and, hence, alter its logic value.) However, this prior art approach has the disadvantage that it takes up valuable space on the integrated circuit.
A totally enclosed cell is provided by published European application 0-433-174-A1, corresponding to U.S. Pat. No. 5,235,541 ("Integrated Circuit Entirely Protected against Ultraviolet Rays"). This application (of common ownership with the present application) describes a totally enclosed two-bit EEPROM cell, in which well diffusions are used to route incoming lines beneath the shallow diffusion at the sidewalls of the metal shield.
The present invention provides a totally enclosed UPROM cell which has a simpler and more compact structure, and has several notable features. This memory cell, in the presently preferred embodiment, uses a conventional EPROM cell architecture (with the control gate overlying the floating gate). Connections for the control gate and the drain (but not the source) are routed underneath the metal enclosure using well diffusions. The source diffusion is simply connected to the metal covering (which is grounded).
For manufacturing reliability, a protection diode is included inside the metal enclosure. This protection diode is a diffusion connected to the control gate, and will be reverse-biased during normal operation. However, this protection diode serves the important purpose of preventing the floating gate from becoming charged up during manufacturing. (Any charge trapped at this stage would be no longer removable by UV radiation.)
According to one embodiment of the disclosed innovations, there is provided: an integrated circuit memory cell which is fully protected from UV radiation, being of a type implemented in MOS technology over a semiconductor substrate, comprising: at least one memory transistor having source and drain diffusions and a channel separating the source and drain, and having at least one gate overlying and insulated from and capacitively coupled to at least a portion of the channel; a metallic shield embedded in the semiconductor substrate and covering the transistor, a diffused region defining a closed loop path on the substrate surface all around the transistor, the shield being peripherally connected to the diffused region in an unbroken fashion, and first and second wells extending in the substrate from the transistor to outside the diffused region, the first of the wells being connected directly to the gate terminal of the transistor.
According to another embodiment of the disclosed innovations, there is provided: an integrated circuit, comprising: a body having a surface portion of substantially monolithic semiconductor material of a first conductivity type; a floating-gate transistor, which includes surface source and drain diffusions of a second conductivity type in the surface portion, a channel in the surface portion separating the source and drain, a floating gate overlying and insulated from and capacitively coupled to at least a portion of the channel, and a control gate overlying and insulated from and capacitively coupled to at least a portion of the floating gate; a protection diode, comprising a surface diffusion of the second conductivity type which is connected to the control gate; a metal shield overlying and completely laterally surrounding the transistor and the protection diode; a first deep diffusion of the second conductivity type connected to the control gate and extending out underneath the metal shield to a gate contact location which is outside the shield; and a second deep diffusion of the second conductivity type connected to the drain and extending out underneath the metal shield to a drain contact location which is outside the shield.
According to another embodiment of the disclosed innovations, there is provided: an integrated circuit, comprising: a body having a surface portion of substantially monolithic semiconductor material of a first conductivity type; a floating-gate transistor, which includes surface source and drain diffusions of a second conductivity type in the surface portion, a channel in the surface portion separating the source and drain, a floating gate overlying and insulated from and capacitively coupled to at least a portion of the channel, and a control gate overlying and insulated from and capacitively coupled to at least a portion of the floating gate; a protection diode, comprising a surface diffusion of the second conductivity type which is connected to the control gate; a metal shield having a top portion which is horizontally extended to overlie the transistor and the protection diode, and a side portion which extends down from the top portion to make contact to the surface in a continuous ring which completely laterally surrounds the transistor, the shield also being connected, separately from the side portion thereof, to a shallow diffusion of the first conductivity type in the surface portion; a first deep diffusion of the second conductivity type connected to the control gate and extending out underneath the metal shield and the shallow diffusion to a gate contact location which is outside the shield; and a second deep diffusion of the second conductivity type connected to the drain and extending out underneath the metal shield and the shallow diffusion to a drain contact location which is outside the shield.
The features and advantages of the inventive circuit will become apparent from the following detailed description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.